The transistor is no longer the bottleneck for AI silicon; power, memory bandwidth and packaging are. That was the premise I opened with on Tuesday, September 22, when I moderated the closing executive panel at the Global Semiconductor Alliance’s U.S. Executive Forum in Menlo Park, California in front of more than 150 semiconductor executives.

The session was titled “Silicon at the Breaking Point: Designing Chips for a World That Can’t Wait.” On stage with me were Paul Cho, president of Samsung Semiconductor; Mark Papermaster, AMD’s chief technology officer; Charlie Kawwas, president of Broadcom’s Semiconductor Solutions Group; and Richard Ho, OpenAI’s vice president of hardware. I’ve spent 35 years in this industry and constructed the premise of the session specifically to start an argument. I didn’t get one. All four of the panelists built on the premise from their first answers onward, and where they took the discussion is the point: The constraint has moved, and so has the job of the chip designer.

(Disclosure: AMD, Broadcom and Samsung are clients of my firm, Moor Insights & Strategy, as are Nvidia and Qualcomm mentioned below.)

Custom Silicon Went From Hyperscaler Hedge To Frontier-Lab Strategy

OpenAI and Broadcom announced a 10-gigawatt collaboration in October 2025, and in June 2026 the pair unveiled Jalapeño , OpenAI’s first chip, which went from initial design to tape-out — the hand-off to manufacturing — in nine months. Ho’s reason for OpenAI building its own part: Power is the limiting factor, and a chip aimed at a known set of workloads can be optimized across models, software and silicon to deliver the most intelligence per watt. I said in June that when chip suppliers take 75%-plus design margins, customers will find other paths, and every major hyperscaler as well as the two biggest model makers are now on those other paths. The panel confirmed my take, with one nuance: Ho framed the custom part as a complement to the merchant GPUs that OpenAI keeps buying, not a replacement for them.

The Unit Of Purchase Is Now The Fleet, Which Changes What Chip Design Means

When I put forward this fleet-centered thesis, the four panelists converged on it. Ho said OpenAI’s unit of purchase isn’t a chip or a rack. It’s the entire fleet across multiple campuses, with power allocated by workload. Kawwas said that a gigawatt to train a cluster is no longer enough; the number is now two to four, and he expects single campuses of five to 10 gigawatts by 2031. When buyers plan in terms of gigawatts, chip design stops being a die decision and becomes a project of system co-design across memory, logic, packaging, networking and power, settled at the level of architecture definition rather than in procurement.

Papermaster’s line was that power is performance. The latest node still delivers a per-watt gain, but it costs far more and takes longer to bring up, so you spend that premium only where it pays off. Most of the power goes to moving data, which is why AMD went to chiplets and 3-D stacking and why he now calls thermal and cooling “job one.” I’ve been saying for more than two years that power, not compute capability, is the binding constraint on AI scaling and that the next three years of silicon will be judged on watts per teraflop. Papermaster’s answer for a general-purpose vendor is flexibility designed in up front, which is why AMD’s Venice CPUs ship in six variants , one aimed at agentic AI.

Memory Moves To Page One Of Every Design

Cho’s answer to which constraint could reorder the industry by 2031 was memory, and he had the best line of the night: Memory used to be one chapter in the computer architecture textbook, and by 2031 it will be the first page of every design. His numbers track UC Berkeley’s “AI and Memory Wall” research: peak server compute is up about 60,000x over 20 years, while DRAM bandwidth is up about 100x. His advice: Work backward from the bandwidth curve, design memory first and bring the memory partner into the architecture phase, not procurement.

I framed the constraint the same way when I interviewed Cho for the Six Five Summit in August : AI infrastructure has become a game of memory bandwidth, power and packaging. My company Signal65’s AMD-sponsored evaluation of AMD’s MI355X against Nvidia’s B200 showed the mechanism: At high concurrency and long context, the larger high-bandwidth memory capacity turned a 17% deficit into a lead of up to 1.96x. Where Cho and I part ways is his claim that HBM is no longer a commodity. I contend that memory built to a JEDEC industry standard is a commodity at the pin. Custom logic base dies under HBM4 stacks and compute-under-memory designs are where strategic memory actually lives, and the clearest example of the latter is the architecture shown in June by Qualcomm.

The Substrate Is The Next Choke Point

Kawwas named another constraint that few people outside packaging talk about. The back-end IC packaging substrate, the layer that carries a chip’s connections out to the board, has been 10 to 15% of a chip’s cost, but he expects it to be the choke point for the next five years. The seven substrate suppliers don’t innovate at foundry pace; the most advanced chips are being designed at part sizes of 10,000 to 15,000 square millimeters, against the 1,000 to 2,000 that the substrate suppliers are used to working with today.

Broadcom’s answer is to put itself into substrate production through a partner facility in Singapore it plans to start using sometime during its fiscal year that ends late in 2027. On the OpenAI program, Kawwas said Broadcom’s tape-out cycle used to take 15 to 18 months, but now it’s nine. Nine months against a competitor’s 12 to 18 months buys you at least one extra generation every three years. My colleague Matt Kimball made the broader point last month: Packaging has moved from the back end of the process to the center of the design.

AI Is In The Design Loop, But Engineers Still Sign Off

Ho said that AI has compressed OpenAI’s design cycle more than his team expected, and that the result is engineers who become “super engineers,” not engineers who get replaced. Papermaster’s rule at AMD is that agentic AI runs the design-space exploration that no human could do by hand, while accountability stays with the human engineer. I wrote in 2020 that AI could be the next killer app in semiconductor design. Six years later, a frontier lab proved the point on its own silicon. The chip design software vendors should read that as a demand signal rather than displacement, because Cadence or Synopsys still has to get these chips to a fab .

What Custom Silicon, HBM Supply And Samsung’s New Texas Fab Still Have to Prove

Three things that emerged from this session I’m keeping on my personal watchlist: First, I can’t name a first-generation custom AI chip that crushed it out of the gate, and I said as much on the Six Five Pod in June ; with that in mind, Jalapeño’s real test will be production tokens at gigawatt scale in 2027, not a tape-out before then. Second, HBM qualification takes about a year, so nine-month design cycles now run faster than memory can be validated. Third, Cho said supply chain resilience is now also a design input decided at architecture definition, not a procurement problem, and pointed to Samsung’s Taylor, Texas fab that is slated to enter customer production in 2027 . Until March, that target date was the end of 2026, so the resilience is set to arrive later than planned, and until Taylor is qualified, a second source exists on paper only.

My advice to anyone defining a part to be delivered in 2028: Seat the memory supplier and the packaging supplier in the architecture review, plan for a qualification cycle that now runs longer than the design cycle and qualify a second geography. The advanced node still delivers, at a price. But the real advantage now goes to whoever co-designs compute, memory, packaging, networking and power from day one, which was the consensus on that stage.