The AI Infra Summit (formerly AI HW Summit) this year was huge, with over 9,000 registered on-site attendees over three packed days of sessions in Santa Clara stretching over six large stages and a show floor that seemed to span miles. Next year will be even bigger, hosted at the San Jose Convention center where the Kisaco event managers (an amazing crew!) are expecting over 12,000 attendees, which is nearly as large as Nvidia GTC!! In fact, several attendees told me they found this event to be even more enlightening than the Nvidia supershow.

With six tracks I could not follow it all, and I will try to keep this short. But reach out if you have any questions! ( Note that Qualcomm and Nvidia are both clients of Cambrian-AI Research .)

Ian Buck, Nvidia VP / General Manager, Hyperscale and HPC, took to the stage on Day 1 to speak the gospel according to Jensen. He presented new benchmarks of the Vera CPU that showed it significantly outperformed AMD Turing CPU on agentic workloads. Vera didn’t just beat Turin by a hair, it blew the AMD part away by some 50-100%. Ian shared data from Clickhouse as well, who commented the that Vera was the fastest CPU they had seen, and had some 30 benchmarks to prove it. I cannot stress enough the importance of CPU performance in agentic AI. While humans take time to read and comprehend the output of an AI query, a CPU agent can consume instantly, and quickly turn that into the next query, increasing the number of turns up to 65 fold per task.

I would note that AMD Exec VP Forrest Norrod showed AMD’s version of the same story on day 3, and AMD claimed better performance than Vera. I sure hope MLPerf or SemiAnalysis can develop some benchmarks for inference processing, just the CPU portion, that everyone can agree on , as this is an increasingly important factor in hardware selection for AI Infrastructure.

In addition to showing how fast Rubin is when coupled with the Groq-based LPX accelerator (more on that below) Ian introduced power management firmware called DSX MaxLPS, which can reduce operational power to enable 40% more AI Factory revenue be applying power policy to over-provisioned GPUs, reducing stranded data center power.

As I reported earlier this week , d-Matrix has teamed up with Nvidia to leverage the Nvidia infrastructure (NVLink Fusion, Vera CPU and the MGX rack) to extend the useful life of Nvidia GPUs in inference as well as give themselves a head start in rack-level systems architecture and beyond. First, though, d-Matrix is partnering with neocloud provider Parasail to support disaggregated inference with Nvidia H200 doing the context processing and the d-Matrix Corsair (now available) processing the decode.

The next-gen d-Matrix Raptor will support stacked DRAM and deliver 10X the performance at 1/10th the power. The following generation in 2028 will support multiple stacked DRAM dies. This looks similar to what Qualcomm is doing with their High Bandwidth Compute (HBC) plans. Both companies believe this could address the memory wall, created by the gap between exponential growth in processors vs. the 2x growth (at best) in memory bandwidth over the last decade.

Raptor will be a solid AI accelerator, for both combined and disaggregated inference processing. The chip is due next year, with full volume production on the MGX version of NVL72. The Go To Market will be based on d-Matrix selling the full rack, and owning the customer relationship.

We have yet to hear a clear rationale from Nvidia as to why they are doing this with d-Matrix when the Groq-based LPX rack is supposed to be shipping in volume this quarter; they seem to be targeting the same problem with somewhat similar solutions. Certainly, the LPX solution supports the full Nvidia software ecosystem and Nvidia engineered integration. Also, we have not yet seen the Nvidia Groq LPX roadmap, and wonder whether it, too, will support stacked DRAM to increase memory capacity at lower power and latencies.

Adding these accelerators to racks of Nvidia GPU’s will deliver industry leading performance and, importantly, extend the lifespan of current or previous GPU investments. I would note that cloud-computing company Nebius Group has announced it will raise rental prices across its range of Nvidia hardware—including chips that are years old—which should relieve concerns about them losing value over time. (Please take note, Mr. Burry.) Adding low latency token generation racks to those GPUs will further enhance and extend their useful lives.

d-Matrix also shared their roadmap of annual releases, the most exciting of which will be Lightening, which will support both NVLink and ESUN (Ethernet Scale-Up Networking) and multi-stacked DRAM dies, which will run models in the 20 trillion parameter range. If we aren’t already on the doorstep of AGI, Lightening will certainly get us there from a hardware perspective.

There was not a lot of new news on the Qualcomm front, understandably so as they will be hosting their annual Snapdragon Summit next week in lovely Maui, Hawaii; I’ll update you with more from there. (Yeah, Maui. Tough job but somebody’s has to do it!) However, Tony Pialis, Qualcomm head of Data Center technologies and former CEO of Qualcomm-acquired Alphawave Semi, updated the audience on the company’s data center roadmap, first unveiled at the company’s investor day conference this summer.

In addition to a new data center CPU and custom chip deals with Meta and Amazon, the centerpiece is the new High Bandwidth Compute technology with stacked DRAM on the logic die, similar to what d-Matrix is planning, which should finally break through the memory wall. This looks simple and easy, but it isn’t; the manufacturing of multiple memory dies on top of logic dies is a daunting challenge.

Mr. Pialis was extremely bullish on Qualcomm’s data center plans and sales pipeline, saying with sincerity that even if he does a terrible job at the helm, the data center business will become Qualcomm’s largest market segment in a few years.

Since we covered this in an article earlier this week , we won’t go into details here, but I wanted to share that the Cognichip booth was packed with eager potential buyers of the company’s physics-informed AI solution stack to accelerate chip design by up to 100 fold.

Chip design has become the limiting factor in many companies chasing AI performance. Jeff Dean, the Google godfather of AI, has recently noted that traditional chip design and fabrication cycles typically take 18 to 30 months, but that AI-powered tools could shorten this to 3 to 6 months. Interestingly, that is precisely what Cognichip intends to enable. Read the article linked above for more information.

While nobody is saying it out loud, the promised land of UALink seems to be DOA, as the Ethernet Scale-up Networking (ESUN), championed by the Open Compute Program (OCP), is coming to market. The ESUN founding membership includes all the big names in AI networking, who are providing an open alternative to NVLink for scale-up.

While the underlying silicon powering the standard—such as Broadcom’s 102.4 Tbps Tomahawk 6 switch series—officially began shipping in production volume in early 2026, the full, native deployment of unified ESUN and UALink open-standard scale-up switch fabrics is bound to a multi-year ecosystem rollout.

Broadcom supports many standard-based efforts to create open networking technologies, including OCI for optical interconnects. As this technology rolls out, “scale-up” will no longer be defined as in-rack, but could become a reality in multi-rack configurations.

Positron, the startup founded by Thiel Fellow Thomas Sohmers, made some big news recently, from a new funding round and a massive installation at Oracle. The current platform is compared against the Nvidia H200 on the company’s website. A better comparison would be against the Blackwell or even the Rubin platform, which should exceed this level of performance but at significantly higher power consumption.

Positron AI, a startup developing chips to run AI models, said last Thursday it has raised $875 million in its latest funding round, more ​than quadrupling its valuation in seven months to $5 billion. Positron also said it ​is ⁠deploying more than 50 racks of Atlas, its first-generation inference system, at Oracle Cloud Infrastructure. This is reportedly the first installation of a startup’s AI chip in a hyperscaler datacenter.

Positron’s next-gen Titan solution can run multi-trillion parameter models entirely in the memory of a single server, with up to 18.4TB of memory per system, supporting up to 32 Trillion parameters per server and a token context window of over 10M tokens. I believe this forecasted capability could be one reason Nvidia has resurfaced its CPX context processing solution based on Rubin.

As part of the recent financing, Forest Baskett of NEA, Gavin Baker of Atreides Management, Thomas Jermoluk from Jim Clark Office and Dylan Patel of SemiAnalysis will join Positron's board of directors.

Well, not really; there were scores of other important presentations I missed! But it will have to suffice for now.

Suffice it to say that the AI industry rate-of-change has shifted into an even higher gear. My net impression is that Nvidia still sets the pace, and everyone else tries to innovate around and within the Nvidia sphere of influence.

Disclosures : This article expresses the author's opinions and

should not be taken as advice to purchase from or invest in the companies mentioned. Cambrian-AI Research is fortunate to have many, if not most, semiconductor firms as our clients, including Blaize, BrainChip, Cadence Design, Cerebras, D-Matrix, Eliyan, Esperanto, Flex, GML, Groq, IBM, Intel, Micron, NVIDIA, Qualcomm Technologies, Si-Five, SiMa.ai, Synopsys, Ventana Microsystems, Tenstorrent and scores of investment clients. For more information, please visit our website at https://cambrian-AI.com .