As I described in a recent article , several chip design startups are working to revolutionize chip design with AI, just as Anthropic’s Claude Code has revolutionized software development. Could we be approaching the day when AI can design a finished chip just from the specifications? With Cognichip’s AI Chip Intelligence (ACI) announcement, we just took a huge step in that direction.

Instead of using agentic AI and Large Language Models (LLMs), Cognichip took a unique approach and developed physics-based AI models to automate each step in chip design. Details will be presented at this week’s AI Infra Summit being held in Santa Clara.

How good is this new approach? Manoher Bommena, a Vice President of Engineering at semiconductor firm Renesas, said “Cognichip’s ACI represents one of the most comprehensive approaches to bringing AI into the contemporary design environment – it simply ‘speaks chip’”. Early results point to a roughly 100 times speedup of chip design, with lower power, higher performance, and lower chip cost.

The company has raised $93 million in total funding from Mayfield Fund, Lux Capital, FPV Ventures, Seligman Ventures, SBI Investment, and Candou Ventures. Let’s dive in.

The Cognichip ACI Full-Stack Design System

Most chip design AI tools today are based either on reinforcement learning, such as physical layout tools, or a wrapper around a Large Language Model (LLM), which are trained on a massive amount of text and a relatively small sample of chip design data. One reason we haven’t seen a model trained on chip design is the lack of available data for training such a model. Chip design details are notoriously well-kept secrets, so there simply isn’t enough public data to train a neural network adequately. Cognichip made a strategic bet and built their foundation models on the experiences of its own design team and synthetic data, taking the data sparsity challenge in semiconductors head-on.

Convinced the industry needed a better solution than wrapping agentic AI around LLMs, the company solved the data problem by staffing a chip design project with experienced engineers. They then complemented that approach with a team of AI scientists to create synthetic data to train the AI models. The company says this “physics-informed” approach will produce better and more cost-efficient results than using models that were trained on languages. The approach is similar to Anthropic training their Claude Code models on software repositories such as github instead of Wikipedia. The company will present more details of the Artificial Chip Intelligence system at the AI Infra Summit this week.

After more than two years in development, ACI is now operational across more than 40 engagements, including at semiconductor companies Renesas and SiTime . Early customer success shows the advantage of the physics model approach. In one such benchmark, a single engineer at a major semiconductor company used ACI to process a 55-page specification, completing micro-architecture, RTL design, functional verification, and power-performance-area (PPA) optimization in just a few days. This work would normally require staffing a full front-end design team and would take roughly 4-5 months to complete.

Enterprise Features in ACI

ACI Enterprise includes many features that enable it for use in the modern design environment, and offers enterprise-grade security and compliance. While the AI models run in a hosted cloud, critical data remains secure in the customers’ data center.

  • Zero-Trust IP Protection : Enterprise design “alpha”—the proprietary architectural intuition that gives a chipmaker its competitive edge—remains strictly inside the customer’s firewall rather than passing into third-party training pipelines.
  • Enterprise-Grade Compliance & Assurance : Validated by an independent SOC 2 Type II examination, featuring continuous control monitoring and zero-trust access controls (SSO/MFA) that satisfy rigorous enterprise audit standards.
  • Granular Client-Side Sovereignty : Empowers engineering teams to restrict data visibility with hardened multi-tenant separation by default and continuous workload monitoring.

ACI And FPGAs for Physical AI

Many physical AI implementations use Field Programmable Gate Arrays (FPGAs), as they enable reconfiguration on the fly as the edge device encounters new realities. However, programming an FPGA can take considerable time and requires rare skills. Consequently, Cognichip is seeing a significant opportunity in speeding FPGA development with ACI. Cognichip ACI can go from whiteboard to working FPGA code in a few hours . By speeding FPGA design, developers can now focus on their application, whether in 5G infrastructure, autonomous automotive systems, or industrial IoT, without being hampered by the traditional steep learning curves of FPGA design.

As the industry matures, we are approaching the time when companies can spend more time on architectural innovation, while the time to develop a new chip is reduced to the point where companies can develop perhaps two to three times more chips for specific applications. We aren’t there yet, but we can now see the goal line.